The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a semiconductor structure containing self-aligned borderless contacts and methods of forming the same.
The formation of electrical contacts to electronic and memory devices is a considerable challenge as the integration density of these devices is increased as a consequence of technology scaling. For example, the projected contact pitch for the 32 nm, 22 nm, and 15 nm nodes are 130 nm, 100 nm, and 80 nm, respectively. In order to fit the contact between adjacent gates, contacts must be made at dimensions approaching the gate length of the device unlike previous technologies where the contacts were many times larger than the gate. Definition of this contact is a lithographic challenge. Alignment of the contact to the source, drain, and gate of the device is critical. In particular, misalignment of the source and drain contacts with respect to the gate can cause electrical shorts, rendering the device inoperable.
Therefore a need exists to overcome the problems with the prior art as discussed above.